1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and particularly a semiconductor integrated circuit having a self-refresh function.
2. Description of the Background Art
Referring to FIG. 13, description will now be given on a self-refresh circuit 900 in an EDO-DRAM (extended data output DRAM).
Self-refresh circuit 900 includes, as shown in FIG. 13, a self-refresh-in circuit 901 which generates a timing signal determining timing of entry in a self-refresh mode (referred to as xe2x80x9ca BBUE signalxe2x80x9d hereinafter), and a self-period timer 902 which issues a self-refresh signal SELF.
Self-refresh-in circuit 901 generates the BBUE signal when tens of microseconds elapse after a CBR (CAS before RAS) signal attains H-level. Self-period timer 902 receives the BBUE signal, and issues self-refresh signal SELF, which is a pulse signal of one shot, every 16 xcexcs.
The CBR signal attains H-level when so-called xe2x80x9cCBR conditionsxe2x80x9d are satisfied. Under the xe2x80x9cCBR conditionsxe2x80x9d, an external column address strobe signal /CAS falls prior to external row address strobe signal /RAS.
Self-refresh-in circuit 901 includes a ring oscillator 903 which issues an oscillation signal xcfx860 having a period of T0 in response to the CRB signal, a double period counter 904 which performs counting based on oscillation signal xcfx860, and a BBUE generating portion 905 which generates the BBUE signal in accordance with the output of double period counter 904.
As shown in FIG. 14, ring oscillator 903 includes an NAND circuit 916, inverters 917#1-917#6 connected in series, an NOR circuit 918 and an inverter 919. NAND circuit 916 receives on its inputs the CBR signal and the output of inverter 917#6. NOR circuit 918 receives on its inputs the BBUE signal and the output of inverter 917#6. Inverter 919 inverts the output of NOR circuit 918, and issues oscillation signal xcfx860. Oscillation signal xcfx860 is at H-level during standby.
Double period counter 904 is a counter of n bits. In the case of n=3, it issues signals fx(0), fx(1) and fx(2) based on oscillation signal xcfx860.
BBUE generating portion 905 includes, as shown in FIG. 15, an NOR circuit 910 which receives output signals fx(O)-fx(2) of double period counter 904, an NAND circuit 911 which receives on its inputs the CBR signal and the output of NOR circuit 910, and an inverter 912 which inverts the output of NAND circuit 911 to issue the BBUE signal.
For example, as shown in FIG. 16, when oscillation signal xcfx860 of period T0 is supplied to double period counter 904, it issues signals fx(0), fx(1) and fx(2) having periods of (2xc3x97T0), (4xc3x97T0) and (8xc3x97T0), respectively. Assuming that BBUE generating portion 905 receives signals fx(0), fx(1) and fx(2) having periods of (2xc3x97T0), (4xc3x97T0) and (8xc3x97T0), respectively, it generates the BBUE signal having a period of (8xc3x97T0=2nxc3x97T0).
In the self-refresh-in circuit 901, when the BBUE signal attains H-level, oscillation signal xcfx860 is fixed to H-level. In the practical operation, therefore, the BBUE signal holds the H-level until the CBR signal attains L-level (i.e., until reset).
Self-period timer 902 shown in FIG. 13 includes a ring oscillator 906 which issues an oscillation signal xcfx861 of a period T1 in response to the BBUE signal, a double period counter 907 which performs a count operation based on oscillation signal xcfx861, and a SELF generating portion 908 which issues self-refresh signal SELF in accordance with the output of double period counter 907.
Ring oscillator 906 is formed of an NAND circuit 916 and inverters 917#1-917#6, as shown in FIG. 17.
Double period counter 907 is a counter of m bits. In the case of m=4, double period counter 907 issues sisals fy(0)-fy(4) based on oscillation signal xcfx861. As shown in FIG. 18, signals fy(0), fy(1), fy(2) and fy(3) have periods of (2xc3x97T1), (4xc3x97T1), (8xc3x97T1) and (16xc3x97T1), respectively.
SELF generating portion 908 has a structure similar to that of foregoing BBUE generating portion 905, and issues self-refresh signal SELF of one shot at H-level when all signals fy(0)-fy(3) attains L-level. Self-refresh signal SELF has a period Ts (self-refresh period) equal to (16xc3x97T1=2nxc3x97T1).
An operation of a conventional semiconductor integrated circuit in a self-refresh mode will now be described with reference to FIG. 19. It is assumed that double period counter 904 issues fx(0)-fx(2), and double period counter 907 issues fy(0)-fy(3).
When external row address strobe signal /RAS falls to L-level after external column address strobe signal /CAS fell to L-level, the CBR signal at H-level representing the fact that the CBR conditions are satisfied is issued (time t0). After (8xc3x97T0), the BBUE signal attains H-level. A period (self-in period) which elapses until the operation enters the self-refresh mode after the CBR signal attains H-level until is equal to (8xc3x97T0).
In response to the above, self-refresh signal SELF is issued. Self-refresh period Ts is equal to (16xc3x97T1). In synchronization with self-refresh signal SELF, internal row address strobe signal (internal RAS) is issued. In response to this internal RAS, the operation of selecting the row in the memory cell array is conducted.
Assuming that T0 is equal to 16 xcexcs and T1 is equal to 1 xcexcs, the BBUE signal attains H-level when 80 xcexcs elapses after the CBR signal attains H-level, and the self-refresh period Ts goes to 16 xcexcs.
In the self-refresh-in circuit, the ring oscillator stops after the BBUE is issued. The self-refresh period is changed by tuning.
In the conventional semiconductor integrated circuit, as already described, each of self-refresh-in circuit 901 and self-period timer circuit 902 includes a ring oscillator and a counter which are independent of those in the other.
However, such independent provision of the ring oscillators and the counters unpreferably increases the layout area of the semiconductor integrated circuit.
Accordingly, the invention provides a semiconductor integrated circuit, which can execute a desired self-refresh operation with a reduced layout area.
A semiconductor integrated circuit according to the invention includes a memory cell array including a plurality of memory cells arranged in rows and columns, and a self-refresh circuit for issuing a self-refresh signal determining a self-refresh period for selection of the row in the memory cell array in a self-refresh mode, the self refresh circuit including a ring oscillator receiving a specific signal and issuing an oscillation signal, a counter receiving the oscillation signal, and issuing count signals of m bits (m: natural number), a pulse signal generating circuit generating a pulse signal based on the count signals of m bits, a self-in signal generating circuit for generating a self-in signal in response to the output of the counter after a predetermined period from entry of the specific signal, and a circuit for generating the self-refresh signal based on the pulse signal based in response to the self-in signal.
According to the semiconductor integrated circuit of the above first aspect, the single ring oscillator is used for determining the self-refresh period and the timing (self-refresh-in period) of entry in the self-refresh mode. Therefore, the layout area can be smaller than that in the prior art.
Preferably, the self-in signal generating circuit includes a self-in-capable counter using one of the count signals of m bits as a basic signal, and issuing count signals of n bits (n: natural number), and a generating circuit for generating the self-in signal based on at least one of the count signals of n bits.
According to the above second aspect, the semiconductor integrated circuit of the first aspect further has such a feature that the self-refresh-in period is determined using, as the basic signal, the counter output used for determining the self-refresh period. Accordingly, the counter for determining the self-refresh period can be smaller than that in the prior art.
In particular, the predetermined period is K times (K relates to the foregoing xe2x80x9cnxe2x80x9d, and is an integer not equal to 2n) larger than the period of the basic signal supplied to the self-in-capable counter.
According to the above third aspect, the semiconductor integrated circuit of the second aspect further has such a feature that the self-refresh-in period is K times (K is an integer not equal to 2n) lager than the basic period. Accordingly, such setting is allowed that the operation can enter the self-refresh mode in accordance with desired timing.
Preferably, the self-in signal generating circuit further includes a timing adjusting circuit having a fuse for issuing adjusting signals of L bits (L: natural number), each of the adjusting signals of L bits has a logical level determined independently of the others in accordance with the state of the fuse, and the generating circuit generates the self-in signal based on a combination of the count signals of n bits and the adjusting signals of L bits.
According to the above fourth aspect, the semiconductor integrated circuit of the second aspect further has such a feature that the fuse and the count value can be combined for fine setting of the self-refresh-in period. Accordingly, setting for entry in the self-refresh mode in accordance with desired timing can be achieved.
Preferably, the predetermined period is substantially J times or (J+0.5) times larger than the self-refresh period (J: integer).
According to the above fifth aspect, the semiconductor integrated circuit of the first aspect further has such a feature that the self-refresh-in period can be J times or (J+0.5) times larger than the self-refresh period (J: integer). Accordingly, setting for entry in the self-refresh mode in accordance with desired timing can be achieved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.